This disclosure relates generally to electronic devices, and in particular but not exclusively, relates to use of a single reference component in a master-slave configuration to provide multiple circuit compensation.
Because high-frequency processors are becoming more sensitive to variations in process, supply voltage, and temperature (P-V-T), it becomes prudent to compensate critical circuits for these variations. For example, on-die termination circuits, input/output (I/O) pre-driver circuits, timing control circuits, etc. are compensated because they affect overshoots, undershoots, signal reflections, timing control (Tco), and signal edge rates. Comparing a resistance of an external resistor to the resistance of an internal compensation circuit is the basis for compensating these critical circuits. Accordingly, for each kind of circuit (e.g., on-die termination circuit, I/O pre-driver circuit, Tco circuit, etc.), a separate external resistor is used to compensate each of the required circuit attributes (such as impedance, slew rate, and timing).
FIG. 1 is a schematic diagram of a circuit compensation technique that uses multiple external resistors. The technique shown in FIG. 1 compensates a critical circuit across P-V-T by using an external resistor R (shown in FIG. 1 as having an example value of 100 Ohms) to match a resistance of a compensation circuit 10 formed on a chip 12. The compensation circuit 10 comprises a plurality of P-channel metal oxide semiconductor (PMOS) transistors, referred to as xe2x80x9ctransistor legs.xe2x80x9d In the example of FIG. 1, there are 32 transistor legs.
Matching the on-chip internal resistance of the compensation circuit 10 to the resistance of the external resistor R is done by having a first finite state machine FSM1 turn on the transistor legs one at a time until the effective on-chip internal resistance is approximately equal to the resistance of the external resistor R. At this moment, a comparator circuit 14 (coupled to the external resistor R, to the compensation circuit 10, and to a voltage supply Vdd) trips, and the number of activated transistor legs in the compensation circuit 10 is recorded by the finite state machine FSM1.
From this number of activated transistor legs, a digital impedance code is generated by the finite state machine FSM1 that represents the matched on-chip internal resistance. The finite state machine FSM1 then provides this impedance code (representing 100 Ohms in the example) to other compensation circuits, such as to other Tco circuits on the chip 12 if the compensation circuit 10 compensated for timing, so that these other compensation circuits can compensate that same circuit attribute.
However, if many different circuits need to be compensated across P-V-T for different circuit attributes, a separate impedance code needs to be generated for each circuit. Thus in FIG. 1, n circuits to be compensated require n external resistors Rx. As is often the case, the resistance of any one of the external resistors Rx (40 Ohms as an example in FIG. 1) needs to be different than the resistance of the external resistor R or the resistances of other external resistors.
As apparent in FIG. 1, compensation of many different circuits requires the use of multiple external resistors R to Rx. The use of multiple external resistors R to Rx increases packaging costs and motherboard costs, since multiple pads (e.g., pad 1 to pad n) or pins must be provided, respectively, for the external resistors R to Rx.